1). Field of the Invention
The present invention relates to semiconductor processing and more particularly to a method of planarizing by polishing a structure which is formed to promote planarization.
2). Discussion of Related Art
Semiconductor chips are manufactured by depositing consecutive layers of a material on a substrate. One or more of these layers are formed on a substrate having an uneven topography. The resulting layer has a number of high surfaces and lower surfaces and oftentimes has to be polished back to remove some of the material of the high surfaces. During polishing of the layer to remove the material of the high surfaces some of the material of the lower surfaces is also removed. The polish rate of the layer is thus reduced because of removal of the material of the lower surfaces. Should less of the material of the lower surfaces be removed, a higher polish rate would result and a more planar polished layer.
FIGS. 1a to 1c illustrate a conventional polishing technique of the aforementioned kind.
FIG. 1a of the accompanying drawings illustrates a semiconductor substrate 10 having a number of members 12a, 12b and 12c formed thereon with gaps 14a and 14b formed between the members. The resulting substrate 16 thus has an uneven topography.
The members 12 may be any members generally found in semiconductor integrated circuits. The members 12 may, for example, be metal or other members requiring an inter-layer dielectric (ILD) over the members 12. The members 12 may, alternatively, be metal members requiring an inter-metal dielectric (IMD) between the members 12. The members 12 may, alternatively, be part of a structure with the gaps 14 etched therein for purposes of forming a shallow-trench isolation (STI) region in the gaps. The members 12 may, alternatively, be of an insulating material and the gaps 14 be gaps which are etched into the insulating material for purposes of forming vias such as tungsten plug vias in the gaps 14. The members 12 may, alternatively, be of an insulating material and the gaps 14 be gaps which are etched into the insulating material for purposes of forming aluminum, aluminum alloy, copper or copper alloy metal lines using a damascene process.
FIG. 1b illustrates the structure of FIG. 1a after a layer 18 of material is formed thereon. The layer 18 has an upper surface 20, which has a profile which is dictated by the topography of the substrate 16. High surfaces 22a, 22b and 22c of the surface 20 are located above the members 12a, 12b, 12c and the surface 20 has lower surfaces 24a and 24b in the region of the gaps 14a, 14b.
FIG. 1c illustrates the structure of FIG. 1b after a polishing step carried out until the members 12a, 12b, 12c are exposed. Polishing causes the high surfaces 22a, 22b and 22c to be removed. However, some of the material of the lower surfaces 24a, 24b is also removed so that topography of the layer 18 before polishing is reflected on the structure after polishing. An upper surface of the structure after polishing thus has a profile with a dish 26a and 26b between each of the respective members 12a, 12b, 12c.
A planarization method is thus required which will result in a faster polish rate and a more planar surface after polishing.